1. Field of the Invention
The present invention relates to a semiconductor logical device which is constructed by field effect transistors, and particularly to an improvement in a switching property of a semiconductor logical device.
2. Prior Art
A development of a semiconductor logical device capable of a high speed operation has been recently required, and a semiconductor logical device formed by gallium arsenide metal Schottky junction type field effect transistors (GaAs MES FET) whose base material is gallium arsenide (GaAs) having a high electron mobility is well known (for example, "IEEE JOURNAL OF SOLID STATE CIRCUIT", VOL. 26, NO. 1, JANUARY 1991).
An inverter circuit which is one example of such a semiconductor logical device is shown in FIG. 4.
This inverter circuit is formed by improvement of a circuit named as SBFL (abbreviation of Super Buffer FET Logic), in which an element 4, which acts as a load of a high impedance by shorting between gate-source of a depletion type field effect transistor (hereinafter referred to as D type FET), is connected to an enhancement type field effect transistor 2 (hereinafter referred to as E type FET), a gate contact of an E type FET 6 forming an output circuit which is connected in series between power supply voltage V.sub.DD and V.sub.SS, and a gate contact of E type FET 2 are commonly connected, and a gate contact of the E type FET 8 and a gate contact of the element 4 are commonly connected. Further, in the inverter circuit, a feedback circuit consisting of a D type FET 10 and a Schottky barrier diode 12, which feedback to the gate contact of the E type FET 8 with respect to the change of voltage at the source contact of the E type FET 8 is provided. When an input signal V.sub.in is applied to the gate contact of the E type FET 2, an inversion output Q is output to an output terminal 14 which is connected to the source contact of the E type FET 8.
When, in the inverter circuit, the threshold voltage of the D type FET 4 is equalled to that of the D type FET 10 and both gate widths are selected to a suitable value in the design, the logical value "H" of the inversion output Q for the input signal V.sub.in of the logical value "L" is clamped to a suitable voltage by the D type FET 10 and unnecessary current which flows into a circuit (not shown) connected to the output terminal 14 is advantageously prevented. Therefore, although the inverter circuit has a large current driving ability at a transition time when the inversion output Q is inverted from the logical value "L" to "H", it has such superior function that the dissipation current can be suppressed to a small value.
However, when the inversion output Q becomes a logical value "L" in the inverter circuit having a feedback circuit shown in FIG. 4, the electric potential of the drain contact of the D type FET 10 becomes low. Thus, the gate-drain internal capacitance C.sub.GD which exists between the drain and the gate of the D type FET 10 is increased, with the result that capacitance to be charged by current which flows from the D type FET 4 is increased at a transition time when the inversion output Q is inverted from the logical value "L" to "H" and the delay of the turn-on time necessary for the charge made a problem of hindrance for high speed operation.